The present invention relates to a clock synchronization system having a duplex arrangement constituted by current and spare use modes. The system is suitable for generating a clock for a base station in a mobile radio communication apparatus, and, more particularly to, a clock synchronization system in which synchronization of a supply clock is improved by switching over operation between current and spare clock generating sections.
A conversational clock synchronization system will be described below with reference to FIG. 5 showing the arrangement of the system and FIGS. 6A to 6C showing the timings at which supply clocks are switched over.
Clock generating sections 40a and 40b in FIG. 5 have the same arrangement. A state signal S41b from the clock generating section 40b is supplied to a terminal 14a of the clock generating section 40a via a state signal line 25 connected to a terminal 13b. Similarly, a state signal S41a from the clock generating section 40a is supplied to a terminal 14b of the clock generating section 40b via a state signal line 24 connected to a terminal 13a.
A network sync signal fs1 is supplied to a terminal 11a of the clock generating section 40a and a terminal 11b of the clock generating section 40b via an external reference clock line 21. In addition, apparatus clocks CLK41a and CLK41b from terminals 12a and 12b of the clock generating sections 40a and 40b are supplied to a clock output terminal 20 via clock lines 22 and 23. One of the apparatus clocks is selected to be a supply clock CLK40 to be supplied to an external circuit, as will be described later.
When the clock generating section 40a is in the current use mode, the state signal S41a is set at "0", and the state signal S41b from the clock generating section 40b is set at "1". When the clock generating section 40b is in the current use mode, the state signal S41b is set at "0", and the state signal S41b from the clock generating section 40b is set at "1". Assume that the clock generating section 40a is in the current use mode, and a current/spare use mode setting signal S41 is set at "1". In order to reverse the relationship in current/spare use mode between the clock generating sections 40a and 40b, the logic of the current use mode setting signal S41 is inverted to be set at "0". As a result, a NAND gate 44, in the clock generating section 40a, which has received the state signal S42a, i.e., the state signal S41b of "1" from the clock generating section 40b, and the setting signal S41 of "0", inverts the state signal S41a to "1" indicating that the clock generating section 40a is in the spare use mode. As described above, when the relationship in current/spare use mode is to be reversed, the logic of the current use mode setting signal S41 is inverted.
This clock synchronization system in a case wherein the first clock generating section 40a is in the current use mode will be described below.
Upon reception of the network sync signal fs1 via the reference clock line 21, an oscillation circuit 41 of the clock generating section 40a generates a clock f.sub.M synchronized with the network sync signal fs1. This clock f.sub.M and the network sync signal fs1 are supplied to a frequency-dividing circuit 42. The frequency-dividing circuit 42 is reset at the leading edge of the network sync signal fs1 to frequency-divide the clock f.sub.M so as to generate an apparatus clock CLK41. The apparatus clock CLK41 and the state signal S42a from the clock generating section 40b are input to a NAND gate 43. Since the clock generating section 40a is in the current use mode, the state signal S42a is at "1", and the NAND gate 43 is enabled. Therefore, the apparatus clock CLK41 passes through the NAND gate 43 to become an apparatus clock CLK41a. The apparatus clock CLK41a is supplied, as the supply clock CLK40, to the clock output terminal 20 via the clock line 22. In this case, the output of the apparatus clock CLK41 generated by the clock generating section 40b is inhibited by the NAND gate 43, and hence the apparatus clock CLK41b is not output from the terminal 12b.
When the clock generating section 40b is in the current use mode, the apparatus clock CLK41b from the clock generating section 40b is supplied, as the supply clock CLK40, to the clock output terminal 20 via the clock line 23.
In a clock generating section for a base station in a mobile radio communication apparatus having current and spare clock generating sections, in order to prevent a phase shift in the waveform of a supply clock when the current and spare clock generating sections are switched over, an apparatus clock generated by the spare clock generating section must always be made to coincide with an apparatus clock generated by the current clock generating section.
The conventional clock synchronization system described above, however, does not have a function of keeping the relationship in clock phase between the apparatus clocks CLK41a and CLK41b from the clock generating sections 40a and 40b constant. For this reason, it is highly possible that spike waveforms appear before and after (near switching over points A and B) switching over of the supply clock CLK40 especially at clock change points, as shown in FIG. 6C, in switching over between the current and spare clock generating sections, i.e., switching over of the apparatus clock CLK41a (in FIG. 6A) from the clock generating section 40a and the apparatus clock CLK41b (in FIG. 6B) from the clock generating section 40b.